MT90823AL1 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT90823AL1 Datasheet PDF : 46 Pages
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MT90823
Data Sheet
Input Stream
Offset
Measurement Result from
Frame Delay Bits
FD11 FD2 FD1 FD0
OFn2
Corresponding
Offset Bits
OFn1 OFn0
DLEn
No clock period shift (Default)
1
0
0
0
0
0
0
0
+ 0.5 clock period shift
0
0
0
0
0
0
0
1
+1.0 clock period shift
1
0
0
1
0
0
1
0
+1.5 clock period shift
0
0
0
1
0
0
1
1
+2.0 clock period shift
1
0
1
0
0
1
0
0
+2.5 clock period shift
0
0
1
0
0
1
0
1
+3.0 clock period shift
1
0
1
1
0
1
1
0
+3.5 clock period shift
0
0
1
1
0
1
1
1
+4.0 clock period shift
1
1
0
0
1
0
0
0
+4.5 clock period shift
0
1
0
0
1
0
0
1
Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) and Frame Delay Bits (FD11, FD2-0)
ST-BUS F0i
CLK
STi Stream
STi Stream
STi Stream
STi Stream
GCI F0i
CLK
Input Stream
Input Stream
Input Stream
Input Stream
Bit 7
Bit 7
Bit 7
Bit 7
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
denotes the 3/4 point of the bit cell
Bit 0
Bit 0
Bit 0
Bit 0
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
denotes the 3/4 point of the bit cell
Figure 5 - Examples for Input Offset Delay Timing
21
Zarlink Semiconductor Inc.
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