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AT90S2313-4PI 查看數據表(PDF) - Atmel Corporation

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AT90S2313-4PI Datasheet PDF : 92 Pages
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Power-on Reset
Table 4. Number of Watchdog Oscillator Cycles
FSTRT
Programmed
Time-out at VCC = 5V
0.28 ms
Unprogrammed
16.0 ms
Number of WDT Cycles
256
16K
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. As
shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer
prevents the MCU from starting until after a certain period after VCC has reached the
Power-on Threshold voltage (VPOT) (see Figure 24). The FSTRT Fuse bit in the Flash
can be programmed to give a shorter start-up time if a ceramic resonator or any other
fast-start Oscillator is used to clock the MCU.
If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via
an external pull-up resistor. By holding the RESET pin low for a period after VCC has
been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a tim-
ing example of this.
Figure 24. MCU Start-up, RESET Tied to VCC.
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
Figure 25. MCU Start-up, RESET Controlled Externally
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
20 AT90S2313
0839IAVR06/02

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