
Status Register
M29F800DT
Table 7. Status Register Bits(1)
Operation
Address
DQ7 DQ6 DQ5 DQ3
DQ2
RB
Program
Program during
Erase Suspend
Any address
Any address
DQ7 Toggle
0
–
DQ7 Toggle
0
–
–
0
–
0
Program Error
Chip Erase
Block Erase
before timeout
Block Erase
Erase Suspend
Erase Error
Any address
DQ7 Toggle
1
–
–
0
Any address
0
Toggle
0
1
Toggle
0
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0 No Toggle 0
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1 No Toggle 0
Erasing Block
1 No Toggle 0
–
Toggle
1
Non-Erasing Block
Data read as normal
1
Good Block address 0
Toggle
1
1 No Toggle 0
Faulty Block address 0
Toggle
1
1
Toggle
0
1. Unspecified data bits should be ignored.
Figure 6. Data Polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
NO DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
FAIL
PASS
AI03598
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