
M29DW323DT, M29DW323DB
Table 8. Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Bank Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Bank Address
DQ7
Toggle
0
–
–
0
Program Error
Bank Address
DQ7
Toggle
1
–
–
0
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Block Erase before
timeout
Erasing Block
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
Toggle
0
0
No Toggle
0
Block Erase
Erasing Block
0
Toggle
0
Non-Erasing Block
0
Toggle
0
1
Toggle
0
1
No Toggle
0
Erase Suspend
Erasing Block
1
No Toggle
0
–
Toggle
1
Non-Erasing Block
Data read as normal
1
Erase Error
Good Block Address
0
Toggle
1
Faulty Block Address
0
Toggle
1
Note: Unspecified data bits should be ignored.
1
No Toggle
0
1
Toggle
0
Figure 8. Data Polling Flowchart
Figure 9. Data Toggle Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
NO DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
FAIL
PASS
AI90194
START
READ DQ6
READ
DQ5 & DQ6
DQ= 6
NO
TOGGLE
YES
NO DQ5
=1
YES
READ DQ6
TWICE
DQ= 6
NO
TOGGLE
YES
FAIL
PASS
AI90195B
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