M25PE80-VMN6TP 查看數據表（PDF） - Numonyx -> Micron

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M25PE80-VMN6TP

8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout

Numonyx -> Micron 

Revision history

14 Revision history

M25PE80

Table 32. Document revision history

Date

Version

Changes

24-Nov-2004 0.1 Initial release.

07-Dec-2004 0.2 4KB software protection granularity extended to sector 15.

SO16W package removed, SO8W package added.

End timing line of tSHQZ modified in Figure 28: Output timing. Plating

10-May-2005 0.3 technology options modified in Table 31: Ordering information scheme.

Minor text changes.

Tables 2 and 3 and Figure 6 for details on the software protection scheme.

Lock register programming sequence detailed in section Write to lock

register (WRLR).

25-Jul-2005

Sections An easy way to modify data, A fast way to modify data, Page

0.4 write (PW) and Page program (PP), updated to explain when using page

write and page program instructions.

Bulk erase cycle time (tBE), page write cycle time (tPW) and page program

cycle time (tPP) updated in Table 22: AC characteristics.

24-Aug-2005 1.0 Version number updated for internet. No document changes.

25-Aug-2005 2.0 Document status updated to preliminary data.

Page program cycle time, tPP, and page write cycle time (n bytes), tPW,

updated in Table 22: AC characteristics. ICC3 modified in Table 20: DC

characteristics.

tSLCH, tCHSL, tCHSH, tSHCH and tBE modified in Table 22: AC

22-Nov-2005 3.0 characteristics.

MLP package renamed. Under Plating technology, blank option removed.

Note 3 to Table 22 modified. Address modified in Figure 6: Block diagram.

Note added to Figure 30 and Figure 32.

Document status promoted from preliminary data to full datasheet status.

Don’t care address bits modified in Note 1 (below Figure 12), Note 1

(below Figure 13), Note 1 (below Figure 15), Note 1 (below Figure 16),

12-May-2006

4

Note 1 (below Figure 18) and Note 1 (below Figure 20).

Small text changes.

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