M25PE40-VMN6TP 查看數據表（PDF） - Numonyx -> Micron

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M25PE40-VMN6TP

4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout

Numonyx -> Micron 

DC and AC parameters

M25PE40

8. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence

including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).

9. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

Figure 26. Serial input timing

S

tCHSL

tSLCH

C

tDVCH

tCHDX

D

MSB IN

tSHSL

tCHSH

tSHCH

tCLCH

LSB IN

tCHCL

High Impedance

Q

AI01447C

Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold

timing

TSL or

W

S

tTHSL

tWHSL

tSHTL

tSHWL

C

D

High Impedance

Q

1. For the differences between devices produced in the two processes, see Important note on page 6.

AI3559

52/62

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