M25PE80-VMN6TP 查看數據表（PDF） - STMicroelectronics

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M25PE80-VMN6TP

8 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

M25PE80

Instructions

Table 11. Not for new design: Lock Registers for the M25PE80 in T7Y process

(see Important note on page 6)

Bit

Bit Name Value

Function

b7-b4

b3

Subsector Lock

Down(1)

b2

Subsector Write

Lock(1)

b1

Sector Lock

Down

b0

Sector Write

Lock

Reserved

This functionality must not be used for new designs, as the

M25PE80 delivered from Feb 2007 will not offer this functionality.

‘1’ The Write Lock and Lock Down Bits cannot be changed. Once a

‘1’ is written to the Lock Down Bit it cannot be cleared to ‘0’ except

by a Reset or power-up.

This functionality must not be used for new designs, as the

‘0’

M25PE80 delivered from Feb 2007 will not offer this functionality.

The Write Lock and Lock Down Bits can be changed by writing

new values to them. (Default value).

This functionality must not be used for new designs, as the

‘1’

M25PE80 delivered from Feb 2007 will not offer this functionality.

Write, Program and Erase operations in this subsector will not be

executed. The memory contents will not be changed.

This functionality must not be used for new designs, as the

‘0’

M25PE80 delivered from Feb 2007 will not offer this functionality.

Write, Program and Erase operations in this subsector are

executed and will modify the subsector contents. (Default value).

The Write Lock and Lock Down Bits cannot be changed. Once a

‘1’ ‘1’ is written to the Lock Down Bit it cannot be cleared to ‘0’,

except by a Reset or power-up.

‘0’

The Write Lock and Lock Down Bits can be changed by writing

new values to them. (Default value).

‘1’

Write, Program and Erase operations in this sector will not be

executed. The memory contents will not be changed.

‘0’

Write, Program and Erase operations in this sector are executed

and will modify the sector contents. (Default value).

1. Valid only for sector 0 and sector 15 (the value ‘0’ is returned for other sectors).

Figure 14. Read Lock Register (RDLR) instruction sequence and data-out Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C

Instruction

24-Bit Address

D

23 22 21 3 2 1 0

MSB

High Impedance

Q

Lock Register Out

76543 210

MSB

AI10783

31/61

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