M25PE10-VMN6P 查看數據表（PDF） - STMicroelectronics

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M25PE10-VMN6P

1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

Instructions

M25PE20, M25PE10

6.2

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

● Power-up

● Write Disable (WRDI) instruction completion

● Page Write (PW) instruction completion

● Page Program (PP) instruction completion

● Write Status Register (WRSR) instruction completion

● Write to Lock Register (WRLR) instruction completion

● Page Erase (PE) instruction completion

● SubSector Erase (SSE) instruction completion

● Sector Erase (SE) instruction completion

● Bulk Erase (BE) instruction completion

Figure 9. Write Disable (WRDI) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

24/60

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