M25PE10-VMN6TG 查看數據表（PDF） - STMicroelectronics

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M25PE10-VMN6TG

1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

Memory organization

Figure 7. M25PE10 block diagram

M25PE20, M25PE10

Reset

TSL or W

S

C

D

Q

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

256 Byte

Data Buffer

Status

Register

1FF00h

1FFFFh

Top 256 Pages can

be made read-only

by using the TSL pin(1)

FFFFh

00000h

256 Bytes (Page Size)

The whole memory array

can be made read-only

on a 64 Kbyte basis

through the Lock

Registers

000FFh

X Decoder

1. These features (in gray) are only available in the T7X process.

AI13295b

20/60

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