M25P40SVMN6TGX 查看數據表（PDF） - Numonyx -> Micron

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M25P40SVMN6TGX

4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P40

Figure 9. Read Identification (RDID) instruction sequence and data-out sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31

C

Instruction

D

Manufacturer Identification

Device Identification

High Impedance

Q

15 14 13 3 2 1 0

MSB

MSB

AI06809b

6.4

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write Status

Register cycle is in progress. When one of these cycles is in progress, it is recommended to

check the Write In Progress (WIP) bit before sending a new instruction to the device. It is

also possible to read the Status Register continuously, as shown in Figure 10.

Table 6. Status Register format

b7

b0

SRWD

0

0

BP2

BP1

BP0

WEL

WIP

6.4.1

6.4.2

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

The status and control bits of the Status Register are as follows:

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to

0 no such cycle is in progress.

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

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