M25P32-VMN6PBA 查看數據表（PDF） - Numonyx -> Micron

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M25P32-VMN6PBA

32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

Revision history

13 Revision history

M25P32

Table 21. Document revision history

Date

Revision

Changes

28-Apr-2003 0.1 Target Specification Document written in brief form

15-May-2003 0.2 Target Specification Document written in full

20-Jun-2003 0.3 8x6 MLP8 and SO16(300 mil) packages added

18-Jul-2003

24-Sep-2003

0.4 tPP, tSE and tBE revised

SO16 package code changed. Output Timing Reference Voltage

0.5

changed.

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added.

04-Dec-2003 0.6

Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. Change of naming

for VDFPN8 package.

10-Dec-2003 1.0 Document promoted to Product Preview

01-Apr-2004

Document promoted to Preliminary Data. Soldering temperature

2.0 information clarified for RoHS compliant devices. Device grade

information clarified

05-Aug-2004 3.0 Device grade information further clarified

01-Oct-2004

Document promoted to mature datasheet. Footnotes removed from P and

4.0 G options in Ordering Information table. Minor wording improvements

made.

01-Apr-2005

Read Identification (RDID), Deep Power-down (DP) and Release from

Deep Power-down and Read Electronic Signature (RES) instructions, and

5.0

Active Power, Standby Power and Deep Power-down modes paragraph

clarified.

01-Aug-2005

Updated Page Program (PP) instructions in Page Programming, Page

6.0

Program (PP) and Table 14: AC characteristics.

23-Jan-2006

Fast Program/Erase mode added and Power-up specified for Fast

Program/Erase mode in Power-up and Power-down section. W pin

changed to W/VPP. (see Write Protect/Enhanced Program supply voltage

(W/VPP) description).

7.0

tVPPHSL added to Table 14: AC characteristics and tPP for Fast

Program/Erase mode added. Figure 27: VPPH timing inserted. Note 2

added below Figure 28 All packages are RoHS compliant. Blank option

removed under Plating Technology in Table 20

10-Feb-2006

VDFPN8 package specifications updated (see Section 11: Package

8.0

mechanical).

MLP8 5 × 6 mm and SO8W packages added (see Section 11: Package

mechanical). VCC supply voltage and VSS ground descriptions added.

Figure 4: Bus Master and memory devices on the SPI bus updated and

28-Nov-2006

9 explanation added below.

Table 9: Absolute maximum ratings: VIO max modified and TLEAD added.

Products in T9HX technology introduced (see Table 15: AC

characteristics (T9HX technology)). Small text changes.

52/54

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