M25P32-VMN6TPBA 查看數據表（PDF） - Numonyx -> Micron

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M25P32-VMN6TPBA

32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P32

6.11

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the Deep Power-down mode). It can also be used as a software

protection mechanism, while the device is not in active use, as in this mode, the device

ignores all Write, Program and Erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power

mode (if there is no internal cycle currently in progress). But this mode is not the Deep

Power-down mode. The Deep Power-down mode can only be entered by executing the

Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to

ICC2, as specified in Table 14).

To take the device out of Deep Power-down mode, the Release from Deep Power-down and

Read Electronic Signature (RES) instruction must be issued. No other instruction must be

issued while the device is in Deep Power-down mode.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction also

allows the Electronic Signature of the device to be output on Serial Data Output (Q).

The Deep Power-down mode automatically stops at Power-down, and the device always

Powers-up in the Standby Power mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 18.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced

to ICC2 and the Deep Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 18. Deep Power-down (DP) instruction sequence

S

01234567

tDP

C

Instruction

D

Stand-by Mode Deep Power-down Mode

AI03753D

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