M24128FDW3TP 查看數據表（PDF） - STMicroelectronics

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M24128FDW3TP

128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM

STMicroelectronics 

Memory organization

3

Memory organization

M24128, M24C64, M24C32

The memory is organized as shown in Figure 7.

Figure 7. Block diagram

WC

E0

Control Logic

E1

E2

SCL

SDA

I/O Shift Register

High Voltage

Generator

Address Register

and Counter

Data

Register

1 Page

X Decoder

AI06899

12/39

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