LTC4069EDC-TRPBF(RevB) 查看數據表（PDF） - Linear Technology

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LTC4069EDC-TRPBF
(Rev.:RevB)

Standalone 750mA Li-Ion Battery Charger in 2 × 2 DFN with NTC Thermistor Input

Linear Technology 

LTC4069

APPLICATIONS INFORMATION

RNOM

=

RCOLD − RHOT

3.266 − 0.5325

=

10k • (2.816 − 0.4086)

3.266 − 0.5325

= 8.8k, 8.87k is the nearest 1% value.

R1

=

10k

•

⎛

⎝⎜

0.5325 ⎞

3.266 − 0.5325⎠⎟

•

(2.816 −

0.4086) − 0.4086

= 604Ω, 604 is the nearest 1% value.

NTC Trip Point Error

When a 1% resistor is used for RHOT, the major error

in the 40°C trip point is determined by the tolerance

of the NTC thermistor. A typical 100k NTC thermistor

has ±10% tolerance. By looking up the temperature

coefficient of the thermistor at 40°C, the tolerance error

can be calculated in degrees centigrade. Consider the

Vishay NTHS0603N01N1003J thermistor, which has a

temperature coefficient of –4%/°C at 40°C. Dividing the

tolerance by the temperature coefficient, ±5%/(4%/°C) =

±1.25°C, gives the temperature error of the hot trip point.

The cold trip point error depends on the tolerance of the

NTC thermistor and the degree to which the ratio of its

value at 0°C and its value at 40°C varies from 6.14 to 1.

Therefore, the cold trip point error can be calculated using

the tolerance, TOL, the temperature coefficient of the

thermistor at 0°C, TC (in %/°C), the value of the thermistor

at 0°C, RCOLD, and the value of the thermistor at 40°C,

RHOT. The formula is:

Temperature

Error(°C) =

⎛ 1+ TOL

⎝⎜ 6.14

•

RCOLD

RHOT

− 1⎞⎠⎟

• 100

TC

For example, the Vishay NTHS0603N01N1003J thermistor

with a tolerance of ±5%, TC of –5%/°C and RCOLD/RHOT

of 6.13, has a cold trip point error of:

Temperature

Error(°C) =

⎛ 1+ 0.05

⎜⎝ 6.14

•

6.13 − 1⎞⎠⎟

−5

• 100

= −0.95°C, 1.05°C

PACKAGE DESCRIPTION

DC Package

6-Lead Plastic DFN (2mm × 2mm)

(Reference LTC DWG # 05-08-1703)

0.675 ±0.05

R = 0.115

TYP

0.56 ± 0.05

4

(2 SIDES)

0.38 ± 0.05

6

2.50 ±0.05

1.15

±0.05

0.61 ±0.05

(2 SIDES)

PACKAGE PIN 1 BAR

OUTLINE TOP MARK

(SEE NOTE 6)

0.25 ± 0.05

0.50 BSC

1.42 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.200 REF

2.00 ±0.10

(4 SIDES)

0.75 ±0.05

0.00 – 0.05

PIN 1

CHAMFER OF

EXPOSED PAD

3

1

(DC6) DFN 1103

0.25 ± 0.05

0.50 BSC

1.37 ±0.05

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

4069fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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