LTC1403AI 查看數據表（PDF） - Linear Technology

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LTC1403AI

Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown

Linear Technology 

LTC1403/LTC1403A

APPLICATIO S I FOR ATIO

Figure 5. Recommended Layout

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1403/LTC1403A, a printed cir-

cuit board with ground plane is required. Layout for the

printed circuit board should ensure that digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital track

alongside an analog signal track. If optimum phase match

between the inputs is desired, the length of the two input

wires should be kept matched.

High quality tantalum and ceramic bypass capacitors

should be used at the VDD and VREF pins as shown in the

Block Diagram on the first page of this data sheet. For

optimum performance, a 10µF surface mount AVX capaci-

tor with a 0.1µF ceramic is recommended for the VDD and

VREF pins. Alternatively, 10µF ceramic chip capacitors

such as Murata GRM235Y5V106Z016 may be used. The

capacitors must be located as close to the pins as possible.

The traces connecting the pins and the bypass capacitors

must be kept short and should be made as wide as

possible.

Figure 5 shows the recommended system ground connec-

tions. All analog circuitry grounds should be terminated at

the LTC1403/LTC1403A GND (Pins 4, 5, 6 and exposed

pad). The ground return from the LTC1403/LTC1403A

(Pins 4, 5, 6 and exposed pad) to the power supply should

be low impedance for noise free operation. Digital circuitry

grounds must be connected to the digital supply common.

In applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feedthrough from the

microprocessor to the successive approximation com-

parator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion or by

using three-state buffers to isolate the ADC data bus.

POWER-DOWN MODES

Upon power-up, the LTC1403/LTC1403A is initialized to

the active state and is ready for conversion. The Nap and

Sleep mode waveforms show the power-down modes for

the LTC1403/LTC1403A. The SCK and CONV inputs con-

trol the power-down modes (see Timing Diagrams). Two

rising edges at CONV, without any intervening rising

edges at SCK, put the LTC1403/LTC1403A. in Nap mode

and the power drain drops from 14mW to 6mW. The

internal reference remains powered in Nap mode. One or

more rising edges at SCK wake up the LTC1403/LTC1403A

for service very quickly, and CONV can start an accurate

conversion within a clock cycle. Four rising edges at

1403af

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