LFEC3E-4QN208I 查看數據表（PDF） - Lattice Semiconductor
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LFEC3E-4QN208I Datasheet PDF : 163 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
tSUCE_EBR
Clock Enable Setup Time to EBR Output
Register
tHCE_EBR
tRSTO_EBR
Clock Enable Hold Time to EBR Output Register
Reset To Output Delay Time from EBR Output
Register
PLL Parameters
tRSTREC
Reset Recovery to Rising Clock
tRSTSU
Reset Signal Setup Time
DSP Block Timing2, 3
tSUI_DSP
Input Register Setup Time
tHI_DSP
Input Register Hold Time
tSUP_DSP
Pipeline Register Setup Time
tHP_DSP
Pipeline Register Hold Time
tSUO_DSP4
Output Register Setup Time
tHO_DSP4
Output Register Hold Time
tCOI_DSP4
Input Register Clock to Output Time
tCOP_DSP4
Pipeline Register Clock to Output Time
tCOO_DSP
Output Register Clock to Output Time
tSUADSUB
AdSub Input Register Setup Time
tHADSUB
AdSub Input Register Hold Time
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode.
4. These parameters include the Adder Subtractor block in the path.
Timing v.G 0.30
-5
Min. Max.
0.18 —
-0.14 —
— 1.47
1.00 —
1.00 —
-0.38 —
0.71 —
3.31 —
0.71 —
5.54 —
0.71 —
— 7.50
— 4.66
— 1.47
-0.38 —
0.71 —
-4
Min. Max.
0.21 —
-0.17 —
— 1.76
1.00 —
1.00 —
-0.30 —
0.86 —
3.98 —
0.86 —
6.64 —
0.86 —
— 9.00
— 5.60
— 1.77
-0.30 —
0.86 —
-3
Min. Max.
0.25 —
-0.20 —
— 2.05
1.00 —
1.00 —
-0.23
1.00
4.64
1.00
7.75
1.00
—
—
—
-0.23
1.00
—
—
—
—
—
—
10.50
6.53
2.06
—
—
Units
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3-17
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