IDT72V3676L15PFG 查看數據表（PDF） - Integrated Device Technology

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IDT72V3676L15PFG

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM

WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

CLKA

1

2

3

4

COMMERCIAL TEMPERATURE RANGE

CLKB

1

2

3

4

RENB

tRSTS

RT1

tRTMS

tRSTH

tRTMH

tENS2

tENH

RTM

EFB

(2)

tREF

(2)

tREF

B0-Bn

tA

Wx

W1

NOTES:

4665 drw31

1. CSB = LOW

2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit

setup procedure. D = 2,048, 4,096 and 8,192 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively.

Figure 30. Retransmit Timing for FIFO1 (IDT Standard Mode)

CLKC

1

2

3

4

CLKA

1

ENA

RT2

RTM

tRSTS

tRTMS

EFA

A0-An

2

3

4

(2)

tREF

tRSTH

tRTMH

Wx

tENS2

tENH

(2)

tREF

tA

W1

4665 drw32

NOTES:

1. CSA = LOW

2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFC will be LOW throughout the Retransmit

setup procedure. D = 2,048, 4,096 and 8,192 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively.

Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode)

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