JS28F128J3C-110 查看數據表（PDF） - Intel

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JS28F128J3C-110

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

To perform a page mode read after any other operation, the Read Array command must be issued to

read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used

to access register information. During register access, only one word is loaded into the page buffer.

10.1.2

Enhanced Configuration Register (ECR)

The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed to

by the Set Enhanced Configuration Register command, and can select between Four-Word Page

mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when

RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set

Enhanced Configuration Register command. The Set Enhanced Configuration Register command

is written along with the configuration register value, which is placed on the lower 16 bits of the

address bus A[15:0]. This is followed by a second write that confirms the operation and again

presents the enhanced configuration register data on the address bus. After executing this

command, the device returns to Read Array mode. The ECR is shown in Table 15, “Enhanced

Configuration Register” on page 38.

Note:

For forward compatibility reasons, if the 8-word Asynchronous Page mode is to be used on J3C, a

Clear Status Register command must be issued after issuing the Set Enhanced Configuration

Register command. See Table 16, “J3C Asynchronous 8-Word Page Mode Command Bus-Cycle

Definition” on page 38 for further details.

Table 15. Enhanced Configuration Register

Res.

Reserved

R

R

ECR ECR

.15 .14

BITS

8W

ECR

.13

R

ECR

.12

R

R

R

R

ECR ECR ECR ECR

.11 .10 .9

.8

DESCRIPTION

ECR[15:14] Reserved

ECR[13]

• “1” = 8Word Page mode

• “0” = 4Word Page mode

ECR[12:0] Reserved

R

ECR

.7

R

R

R

R

R

R

R

ECR ECR ECR ECR ECR ECR ECR

.6

.5

.4

.3

.2

.1

.0

NOTES

Reserved for Future Use. Set to 0 until further

notice.

Reserved for Future Use. Set to 0 until further

notice.

NOTE: Any reserved bits should be set to 0.

Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition

Command

Set Enhanced

Configuration Register

(Set ECR)

Bus

Cycles

Req’d.

First Bus Cycle

Oper Addr(1) Data

Second Bus Cycle

Oper Addr(1) Data

Third Bus Cycle

Oper Addr(1) Data

3

Write

ECD

0x60 Write ECD 0x04 Write

X

0x50

NOTE: X = Any valid address within the device. ECD = Enhanced Configuration Register Data.

38

Datasheet

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