DSPIC30F9013AT-30E/ML 查看數據表（PDF） - Microchip Technology
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DSPIC30F9013AT-30E/ML Datasheet PDF : 220 Pages
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dsPIC30F3014/4013
FIGURE 17-1:
BUFFERS
TXB0(2)
Message
Queue
Control
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
TXB1(2)
TXB2(2)
Acceptance Mask
RXM0(2)
A
c
Acceptance Filter
c
RXF0(2)
e
p
t
Acceptance Filter
RXF1(2)
Acceptance Mask
RXM1(2)
Acceptance Filter
RXF2(2)
Acceptance Filter
A
RXF3(2)
c
c
Acceptance Filter
e
RXF4(2)
p
t
Acceptance Filter
RXF5(2)
Transmit Byte Sequencer
R(2)
R(2)
X
Identifier
M
Identifier
X
B
A
B
0
B
1
Data Field
Data Field
PROTOCOL
ENGINE
Transmit Shift
CRC Generator
Receive Shift
CRC Check
Receive
Error
Counter
Transmit
Error
Counter
RERRCNT
TERRCNT
Err Pas
Bus Off
Protocol
Finite
State
Machine
Transmit
Logic
CiTX(1)
Note 1: i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2).
2: These are conceptual groups of registers, not SFR names by themselves.
Bit
Timing
Logic
CiRX(1)
Bit Timing
Generator
DS70138E-page 106
© 2007 Microchip Technology Inc.
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