CS8427-CS 查看數據表（PDF） - Cirrus Logic
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CS8427-CS Datasheet PDF : 59 Pages
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CS8427
19.3.5 Jitter Attenuation
Shown in Figure 33, Figure 34, Figure 35, and Fig-
ure 36 are jitter attenuation plots for the various re-
visions of the CS8427 when used with the
appropriate external PLL component values (as
5
noted in Table 7). The AES3 and IEC60958-4
specifications do not have allowances for locking
to sample rates less than 32 kHz or for locking to
the ILRCK input. These specifications state a max-
imum of 2 dB jitter gain or peaking.
5
0
0
−5
−5
−10
−10
−15
−15
−20
−20
10−1
100
101
102
103
104
105
10−1
100
101
102
103
104
105
Jitter Frequency (Hz)
Jitter Frequency (Hz)
Figure 33. Revision A
Figure 34. Revision A1
5
0
−5
−10
−15
−20
−25
10−1
100
101
102
103
104
Jitter Frequency (Hz)
Figure 35. Revision A2 using A1 values
5
0
−5
−10
−15
−20
−25
105
10−1
100
101
102
103
104
105
Jitter Frequency (Hz)
Figure 36. Revision A2 using A2* values
58
DS477F3
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