CS8422 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS8422

24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver

Cirrus Logic 

CS8422

Pin Name

RX_SEL

TX_SEL

SDOUT1

SAOF

MS_SEL

RMCK

MCLK_OUT

TX/U

C

NV/RERR

V/AUDIO

Description

Selects Active AES3 RX Input

Selects RX Input to be output on

TX pin

Enables or Disables De-emphasis

Auto-detect

Selects data format for SDOUT1

& SDOUT2

Selects master/slave and clock

configuration for SDOUT1&

SDOUT 2

Selects master clock source for

SDOUT1 serial port

Selects master clock source for

the SRC

Selects TX pass-through output or

incoming U data output

Selects Software or Hardware

Mode

Selects error signal output on

NV/RERR

Selects either incoming Validity

data output or AUDIO indicator

output

Pin Configuration

Connected to GND

Connected to VL

Connected to GND

Connected to VL

No pull-up on SDOUT1

20 k pull-up on SDOUT1

Selection

RXP0/RXN0 is active

RXP1/RXN1 is active

RXP0/RXN0 to TX

RXP1/RXN1 to TX

De-emphasis Auto-detect

Enabled

De-emphasis Auto-detect

Disabled

See Table 4 on page 41

See Table 5 on page 41

No pull-up on RMCK

20 k pull-up on RMCK

No pull-up on MCLK_OUT

20 k pull-up on MCLK_OUT

No pull-up on U

20 k pull-up on U

No pull-up on C

20 k pull-up on C

No pull-up on RERR/NVERR

20 k pull-up on RERR/NVERR

20 k pull-down on V/AUDIO

20 k pull-up on V/AUDIO

XTI-XTO

RMCK

Ring Oscillator

PLL Clock

TX Pass-through

U Data Output

Software Mode

Hardware Mode

NVERR

RERR

Validity data output

AUDIO indicator output

Table 3. Hardware Mode Control Settings

8.1 Hardware Mode Serial Audio Port Control

The CS8422 uses the resistors attached to the MS_SEL and SAOF pins to determine the modes of opera-

tion for its serial output ports. After RST is released, the resistor value and condition (VL or GND) are

sensed. This operation will take approximately 4 ms to complete. The SRC_UNLOCK pin will remain high

and both SDOUT pins will be muted until the mode detection sequence has completed. After this, if all clocks

are stable, SRC_UNLOCK will be brought low when audio output is valid and normal operation will begin.

The resistor attached to each mode selection pin should be placed physically close to the CS8422. The end

of the resistor not connected to the mode selection pins should be connected as close as possible to VL and

GND to minimize noise. Table 4 and Table 5 show the pin functions and their corresponding settings.

Table 4 shows the Hardware Mode options for output serial port format and the required SAOF pin config-

urations. In the case of SDOUT2, the output resolution depends on the resolution of the incoming AES3-

compatible data. In Right-Justified Modes, the serial format word-length will be equal to the AES3 input data

resolution. The exception is the case where Right-Justified Mode is selected and the AES3 input word-

length is an odd number of bits. In this case, the SDOUT2 word-length will be zero-stuffed to be 1 bit longer

then the AES3 input word-length (example: a 19-bit AES3 input word will result in an 20-bit right-justified

serial format). For a more detailed description of serial formats, refer to Section 5. on page 24.

Table 5 shows the Hardware Mode master/slave and clock options for both serial ports, and the required

MS_SEL pin configurations. For SDOUT1, when the serial port is set to master mode, the master clock ratio

40

DS692F1

Share Link: