CS8420-DSZR 查看數據表（PDF） - Cirrus Logic

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CS8420-DSZR

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

16.3.2 Locking to the RXP/RXN Receiver Inputs

CS8420 parts that are configured to lock to only the RXP/RXN receiver inputs should use the external

PLL component values listed in Table 18 and Table 19. Values listed for the 32 to 96 kHz Fs range will

have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best

output jitter performance.

Revision

D

D1

RFILT (kΩ)

0.909

CFILT (μF)

1.8

CRIP (nF)

33

PLL Lock Time (ms)

56

0.4

0.47

47

60

Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz

Revision

D

D1

RFILT (kΩ)

3.0

1.6

CFILT (μF)

0.047

0.33

CRIP (nF)

2.2

4.7

PLL Lock Time (ms)

35

35

Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz*

* Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for receiver

jitter tolerance should use these component values. Please note that the AES3 and IEC60958 specifica-

tions do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input.

Also note that many factors can affect jitter performance in a system. Please follow the circuit and layout

recommendations outlined previously.

16.3.3 Locking to the ILRCK Input

CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component val-

ues listed in Table 20. Note that parts that need to lock to both ILRCK and RXP/RXN should use

these values. Values listed for the 32 to 96 kHz Fs range will have the highest corner frequency jitter at-

tenuation curve, take the shortest time to lock, and offer the best output jitter performance.

Fs Range

Revision (kHz) RFILT (kΩ) CFILT (μF) CRIP (nF) PLL Lock Time (ms)

D

8 to 96

1.3

2.7

62

120

D

32-96

5.1

0.15

3.9

70

D1

8 to 96

0.3

1.0

100

120

D1

32-96

0.6

0.22

22

70

Table 20. Locking to the ILRCK Input

DS245F4

89

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