CS8416-CSZ 查看數據表（PDF） - Cirrus Logic

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产品描述 (功能)

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CS8416-CSZ

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

18.2.5 Jitter Attenuation

CS8416

Shown in Figure 25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi-

mum of 2 dB jitter gain or peaking.

4

2

0

2

4

6

8

10

12

101

100

101

102

103

104

105

J itter F requency (Hz)

Figure 25. Jitter Attenuation Characteristics of PLL

DS578F3

55

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