CS8415A-CSR 查看數據表（PDF） - Cirrus Logic

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CS8415A-CSR

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

15.APPENDIX C: PLL FILTER

CS8415A

15.1 General

An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 18

is a simplified diagram of the PLL in these parts. When the PLL is locked to an AES3 input stream, it is up-

dated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, FS. When the

PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn’t affect jitter.

There are some applications where low-jitter in the recovered clock, presented on the RMCK pin, is impor-

tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown

in Figure 21, Figure 22, Figure 23, and Figure 24. In addition, the PLL has been designed to only use the

preambles of the AES3 stream to provide lock update information to the PLL. This results in the PLL being

immune to data-dependent jitter affects because the AES3 preambles do not vary with the data.

The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.

If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will

only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample

rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8415A

clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its

wide lock range mode and re-acquire a new nominal center sample rate.

INPUT

Phase

Comparator

and Charge Pump

RFLT

CFLT

VCO

CRIP

RMCK

÷N

Figure 18. PLL Block Diagram

DS470F4

41

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