CS8900A-1 查看數據表（PDF） - Cirrus Logic
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CS8900A-1 Datasheet PDF : 138 Pages
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CS8900A
Crystal LAN™ Ethernet Controller
Enter Exam ple H ere
Frame 1
Frame 2
Frame 3
Entering this exam ple, the receive buffer is em pty and the
DM A Fram e Count (PacketPage base + 0028h) is zero.
Fram e 1 received and com pletely stored in on-chip RAM .
Fram e 2 received and com pletely stored in on-chip RAM .
At this point, the CS8900A does not have sufficient buffer
space for another com plete large fram e (1518 bytes).
Fram e 3 starts to be received and passes the DA filter.
This activates Auto-Switch DM A.
Fram e 1 is placed in host m em ory via DM A freeing
space for the incom ing Fram e 3. The CS8900A updates
the DM A Fram e Count, DM A Start of Fram e and DM A
Byte C ount registers. It then sets the RxD M A D M AF ram e
bit and generates an interrupt.
Frame 2 is placed in host m em ory via DM A and the
CS8900A updates the DM A registers.
The host responds to the RxDM AFram e interrupt, and
reads the Fram e C ount register, which is cleared w hen
read. Since there are no receive interrupts pending, the
CS8900A exits DM A (assum es Fram e 3 is still com ing in).
Fram e 3 is com pletely buffered in on-chip RAM , and
awaits processing by the host.
T im e
Receive DMA used
during this tim e.
Exit Exam ple
Figure 27. Example of Auto-Switch DMA
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