CS8411-IS 查看數據表（PDF） - Cirrus Logic

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CS8411-IS

Digital Audio Interface Receiver

Cirrus Logic 

CS8411 CS8412

Error and Frequency Reporting

When SEL is low, error and received frequency in-

formation are selected. The error information is en-

coded on pins E2, E1, and E0, and is decoded as

shown in Table 5. When an error occurs, the corre-

sponding error code is latched. Clearing is then ac-

complished by bringing SEL high for more than

eight MCK cycles. The errors have a priority asso-

ciated with their error code, with validity having

the lowest priority and no lock having the highest

priority. Since only one code can be displayed, the

error with the highest priority that occurred since

the last clearing will be selected.

E2 E1 E0

00 0

00 1

01 0

01 1

10 0

10 1

11 0

11 1

Error

No Error

Validity Bit High

Reserved

Slipped Sample

CRC Error (PRO only)

Parity Error

Bi-Phase Coding Error

No Lock

Table 5. Error Decoding

The validity flag indicates that the validity bit for a

previous sample was high since the last clearing of

the error codes. The slipped sample error can only

occur when FSYNC and SCK of the audio serial

port are inputs. In this case, if FSYNC is asynchro-

nous to the received data rate, periodically a stereo

sample will be dropped or reread depending on

whether the read rate is slower or faster than the re-

ceived data rate. When this occurs, the slipped sam-

ple error code will appear on the ’E’ pins. The CRC

error is updated at the beginning of a channel status

block, and is only valid when the professional for-

mat of channel status data is received. This error is

indicated when the CS8412 calculated CRC value

does not match the CRC byte of the channel status

block or when a block boundary changes (as in re-

moving samples while editing). The parity error oc-

curs when the incoming sub-frame does not have

even parity as specified by the standards. The bi-

phase coding error indicates a biphase coding vio-

lation occurred. The no lock error indicates that the

PLL is not locked onto the incoming data stream.

Lock is achieved after receiving three frame pre-

ambles then one block preamble, and is lost after

not receiving four consecutive frame preambles.

The received frequency information is encoded on

pins F2, F1, and F0, and is decoded as shown in Ta-

ble 6. The on-chip frequency comparator compares

the received clock frequency to an externally sup-

plied 6.144 MHz clock which is input on the FCK

pin. The ’F’ pins are updated three times during a

channel status block including prior to the rising

edge of CBL. CBL may be used to externally latch

the ’F’ pins. The clock on FCK must be valid for

two thirds of a block for the ’F’pins to be accurate.

F2 F1 F0

00 0

00 1

01 0

01 1

10 0

10 1

11 0

11 1

Sample Frequency

Out of Range

48 kHz ± 4%

44.1 kHz ± 4%

32 kHz ± 4%

48 kHz ± 400 ppm

44.1 kHz ± 400 ppm

44.056 kHz ± 400 ppm

32 kHz ± 400 ppm

Table 6. Sample Frequency Decoding

Channel Status Reporting

When SEL is high, channel status is displayed on

C0, and Ca-Ce for the channel selected by CS12. If

CS12 is low, channel status for sub-frame1 is dis-

played, and if CS12 is high, channel status for sub-

frame 2 is displayed. The contents of Ca-Ce depend

upon the C0 professional/consumer bit. The infor-

mation reported is shown in Table 7.

Pin

Professional

C0

0 (low)

Ca

C1

Cb

EM0

Cc

EM1

Cd

C9

Ce

CRCE

Consumer

1 (high)

C1

C2

C3

ORIG

IGCAT

Table 7. Channel Status Pins

DS61F1

27

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