CS8406-CS 查看數據表（PDF） - Cirrus Logic
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CS8406-CS Datasheet PDF : 43 Pages
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CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
Symbol Min Typ Max
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 9)
fsck
tcsh
tcss
tscl
(Note 10)
tsch
tdsu
(Note 11)
tdh
tpd
tr1
tf1
(Note 12)
tr2
(Note 12)
tf2
0
-
6.0
1.0
-
-
20
-
-
66
-
-
MAX ((1/256 FS + 8), 66)
40
-
-
15
-
-
-
-
50
-
-
25
-
-
25
-
-
100
-
-
100
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate.
10. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For fsck < 1 MHz.
CS
t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
CDOUT
t dsu
t dh
t pd
Figure 3. SPI Mode timing
DS580F1
9
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