CS8406-DS 查看數據表（PDF） - Cirrus Logic
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CS8406-DS Datasheet PDF : 43 Pages
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CS8406
7. CONTROL PORT REGISTER SUMMARY
Addr
Function
(HEX)
00 Reserved
01 Control 1
02 Control 2
03 Data Flow Control
04 Clock Source Control
05 Serial Input Format
06 Reserved
07 Interrupt 1 Status
08 Interrupt 2 Status
09 Interrupt 1 Mask
0A Interrupt 1 Mode (MSB)
0B Interrupt 1 Mode (LSB)
0C Interrupt 2 Mask
0D Interrupt 2 Mode (MSB)
0E Interrupt 2 Mode (LSB)
0F-11 Reserved
12 CS Data Buffer Control
13 U Data Buffer Control
1D-1F Reserved
20-37 C or U Data Buffer
7F ID and Version
7
0
0
0
0
0
SIMS
0
TSLIP
0
TSLIPM
TSLIP1
TSLIP0
0
0
0
0
0
0
0
ID3
6
0
VSET
0
TXOFF
RUN
SISF
0
0
0
0
0
0
0
0
0
0
0
0
0
ID2
5
0
0
0
AESBP
CLK1
SIRES1
0
0
0
0
0
0
0
0
0
0
BSEL
0
0
ID1
4
0
MUTEAES
0
0
CLK0
SIRES0
0
0
0
0
0
0
0
0
0
0
0
UD
0
ID0
3
0
0
0
0
0
SIJUST
0
0
0
0
0
0
0
0
0
0
0
UBM1
0
VER3
2
0
INT1
MMT
0
0
SIDEL
0
0
EFTU
0
0
0
EFTUM
EFTU1
EFTU0
0
EFTCI
UBM0
0
VER2
1
0
INT0
MMCST
0
0
SISPOL
0
EFTC
0
EFTCM
EFTC1
EFTC0
0
0
0
0
CAM
0
0
VER1
0
0
TCBLD
MMTLR
0
0
SILRPOL
0
0
0
0
0
0
0
0
0
0
0
EFTUI
0
VER0
Table 1. Control Register Map Summary
Notes:
Reserved registers must not be written to during normal operation. Some reserved registers are used
for test modes, which can completely alter the normal operation of the CS8406.
22
DS580F1
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