CS7615 查看數據表（PDF） - Cirrus Logic

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CS7615

CCD Imager Analog Processor

Cirrus Logic 

CS7615

FR- Reset gate clock pulse for CCD, PIN 20.

Connect directly to CCD. FR is a rising pulse.

H1- Horizontal shift register clock #1, PIN 23.

Connect directly to CCD.

H2- Horizontal shift register clock #2, PIN 24.

Connect directly to CCD.

V4X- Vertical shift register clock, PIN 25.

Connects to vertical driver.

VH3X- Charge read out pulse, PIN 26.

Connect to vertical driver.

V3X- Vertical shift register clock, PIN 27.

Connects to vertical driver.

VH1X- Charge read out pulse, PIN 28.

Connect to vertical driver.

V1X- Vertical shift register clock, PIN 29.

Connects to vertical driver.

V2X- Vertical shift register clock, PIN 30.

Connects to vertical driver.

OFDX- Charge sweep out pulse for shutter control, PIN 31.

Connect to vertical driver. OFDX is a falling pulse.

HCLK- Horizontal line frequency clock, PIN 34.

Connect to DC-DC converter. HCLK is a falling pulse when it is in “HREF” output mode.

Mosaic Data and clock Outputs

DO[0..9] - Digital Mosaic Outputs.

CMOS level Mosaic coded CCD output data.

32

DS231PP6

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