CS61584A-IQ5 查看數據表（PDF） - Cirrus Logic

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CS61584A-IQ5

Dual T1/E1 Line Interface

Cirrus Logic

CS61584A-IQ5 Datasheet PDF : 54 Pages

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DS261PP5

CS61584A

10.1 JTAG Data Registers (DR)

The test data registers are the Boundary-Scan Reg-

ister (BSR), the Device Identification Register

(DIR), and the Bypass Register (BR).

Boundary Scan Register: The BSR is connected in

parallel to all the digital I/O pins, and provides the

mechanism for applying/reading test patterns

to/from the board traces. The BSR is 62 bits long

and is initialized and read using the instruction

SAMPLE/PRELOAD. The bit ordering for the

BSR is the same as the top-view package pin out,

beginning with the LOS1 pin and moving counter-

clockwise to end with the PD1 pin as shown in Ta-

ble 10. Note that the analog, oscillator, power,

ground, CLKE/IPOL, and MODE pins are not in-

cluded as part of the boundary-scan register.

The input pins require one bit in the BSR and only

one J-TCK cycle is required to load test data for

each input pin.

The output pins have two bits in the BSR to define

output high, output low, or high impedance. The

first bit (shifted in first) selects between an output-

enabled state (bit set to 1) or high-impedance state

(bit set to 0). The second bit shifted in contains the

test data that may be output on the pin. Therefore,

two J-TCK cycles are required to load test data for

each output pin.

The bi-directional pins have three bits in the BSR

to define input, output high, output low, or high im-

pedance. The first bit shifted into the BSR config-

ures the output driver as high-impedance (bit set to

0) or active (bit set to 1). The second bit shifted into

the BSR sets the output value when the first bit is 1.

The third bit captures the value of the pin. This pin

may have its value set externally as an input (if the

first bit is 0) or set internally as an output (if the

first bit is 1). To configure a pad as an input, the J-

TDI pattern is 0X0. To configure a pad as an out-

put, the J-TDI pattern is 1X1. Therefore, three J-

TCK cycles are required to load test data for each

bi-directional pin.

When JTAG testing is conducted in Host mode, the

polarity of the INT pin is determined by the state of

the IPOL pin. The JTAG BSR should configure the

INT pin as an input in Hardware mode and as an

output in Host mode.

Device Identification Register: The DIR provides

the manufacturer, part number, and version of the

CS61584A. This information can be used to verify

that the proper version or revision number has been

used in the system under test. The DIR is 32 bits

long and is partitioned as shown in Table 11. Data

from the DIR is shifted out to J-TDO LSB first.

BSR Bits

0-2

3-5

8-9

10 - 11

12 - 13

15 - 17

19 - 21

22 - 24

25 - 27

28 - 30

31 - 33

34 - 36

37 - 39

40 - 42

45 - 46

47 - 48

49 - 50

53 - 55

56 - 58

Pin Name

LOS1, SAD6

TNEG1, AIS1

TPOS1, TDATA1

TCLK1

RNEG1, BPV1

RPOS1, RDATA1

RCLK1

ATTEN1, CS

RLOOP1, INT

RLOOP2, SCLK, RD(DS)

LLOOP, SDO, AD0

TAOS1, SDI, AD1

TAOS2, SPOL, AD2

CON01, AD3

CON02, AD4

CON11, AD5

CON12, AD6

CON21, AD7

CON22, ALE(AS)

CON31, WR(R/W)

RCLK2

RPOS2, RDATA2

RNEG2, BPV2

TCLK2

TPOS2, TDATA2

TNEG2, AIS2

LOS2, SAD7

CON32, BTS

PD2, SAD5

PD1, SAD4

Pad Type

bi-directional

input

output

input

bi-directional

input

bi-directional

input

output

input

bi-directional

input

Table 10. Boundary Scan Register

DDS2S6216P1PF15

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