CS61574A-IL1Z 查看數據表（PDF） - Cirrus Logic

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CS61574A-IL1Z

T1/E1 Line Interface

Cirrus Logic 

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CS61574A CS61575



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Figure 12. Typical Jitter Transfer Function

The FIFO in the jitter attenuator is designed to

prevent overflow and underflow. If the jitter am-

plitude becomes very large, the read and write

pointers may get very close together. Should they

attempt to cross, the oscillator’s divide by four

circuit adjusts by performing a divide by 3 1/2 or

divide by 4 1/2 to prevent the overflow or under-

flow. During this activity, data will never be lost.

The difference between the CS61575 and

CS61574A is the depth of the FIFO in the jitter

attenuator. The CS61575 has a 192-bit FIFO

which allows it to attenuate large amplitude, low

frequency jitter as required by AT&T 62411 (e.g.,

28 UIpp @ 300 Hz). This makes the CS61575

ideal for use in T1 Customer Premises Equipment

which must be compatible with AT&T 62411 re-

quirements. In single-line Stratum 4, Type II

systems which are loop-timed, he CS61575 re-

covered clock can be used as the transmit clock

eliminating the need for an external system clock

synchronizer. In Stratum 4, Type I systems which

transfer timing and require a clock synchronizer,

the CS61575 simplifies the design of the synchro-

nizer by absorbing large amplitude low frequency

jitter before it reaches the synchronizer.

The CS61574A has a 32-bit FIFO which allows it

to absorb jitter with minimum data delay in T1

and E1 switching or transmission applications.

The CS61574A will tolerate large amplitude jitter

by tracking rather than attenuating it, preventing

data errors so that the jitter may be absorbed in

external frame buffers. With large amplitude input

jitter, the CS61574A jitter transfer function may

exhibit some jitter peaking, but will offer per-

formance comparable to the CS61574.

The jitter attenuator may be bypassed by pulling

XTALIN to RV+ through a 1 kΩ resistor and pro-

viding a 1.544 MHz (or 2.048 MHz) clock on

ACLKI. RCLK may exhibit quantization jitter of

approximately 1/13 UIpp and a duty cycle of ap-

proximately 30% (70%) when the attenuator is

disabled.

Local Loopback

Local loopback is selected by taking LLOOP, pin

27, high or by setting the LLOOP register bit via

the serial interface.

The local loopback mode takes clock and data

presented on TCLK, TPOS, and TNEG (or

TDATA), sends it through the jitter attenuator and

outputs it at RCLK, RPOS and RNEG (or

RDATA). If the jitter attenuator is disabled, it is

bypassed. Inputs to the transmitter are still trans-

mitted on TTIP and TRING, unless TAOS has

been selected in which case, AMI-coded continu-

ous ones are transmitted at the TCLK frequency.

The receiver RTIP and RRING inputs are ignored

when local loopback is in effect.

DS154F3

15

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