CS5581(2007) 查看數據表（PDF） - Cirrus Logic
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CS5581 Datasheet PDF : 32 Pages
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8/22/07
14:46
CS5581
SWITCHING CHARACTERISTICS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.
Parameter
Symbol Min
Typ
Max Unit
Master Clock Frequency
Internal Oscillator XIN
12
14
16
MHz
External Clock fclk
0.5
16
16.2 MHz
Master Clock Duty Cycle
40
-
60
%
Reset
RST Low Time
(Note 8)
tres
1
-
-
µs
RST rising to RDY falling
Internal Oscillator twup
External Clock
-
120
-
µs
-
1536
- MCLKs
Calibration
CAL pulse width
(Note 9, 10)
tpw
4
-
- MCLKs
CAL high setup time to RST rising
(Note 9, 10)
tccw
0
-
-
ns
Calibration Time
RST rising (CAL high) to RDY falling
tscl
-
85218
- MCLKs
Calibration Time
CAL rising (RST high) to RDY falling
tcal
-
85218
- MCLKs
Conversion
CONV Pulse Width
tcpw
4
-
- MCLKs
BP/UP setup to CONV falling
(Note 11)
tscn
0
-
-
ns
CONV low to start of conversion
tscn
-
-
2 MCLKs
Perform Single Conversion (CONV high before RDY falling)
tbus
20
-
- MCLKs
Conversion Time
(Note 12)
Start of Conversion to RDY falling tbuh
-
-
84 MCLKs
8. Reset must not be released until the power supplies and the voltage reference are within specification.
9. CAL must remain high until RDY falls at the end of the calibration time.
10. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration
will be performed. CAL must remain high until RDY falls.
11. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
12. If CONV is held low continuously, conversions occur every 80 MCLK cycles.
If RDY is tied to CONV, conversions will occur every 82 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 84 MCLKs.
RDY falls at the end of conversion.
6
DS796A1
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