CS5571 查看數據表（PDF） - Cirrus Logic

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CS5571

±2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

10:56

CS5571

SCLK – Serial Clock Input/Output, Pin 23

The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK

determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC

mode, the SCLK frequency will be determined by the master clock frequency of the converter

(either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.

If SCLK is an output (SMODE = VL), it will be in a high-impedance state when CS is high.

RDY – Ready, Pin 24

If CONV is low the converter will immediately start a conversion and RDY will remain high until

the conversion is completed. At the end of any conversion RDY falls to indicate that a conver-

sion word has been placed into the serial port. RDY will return high after all data bits are shifted

out of the serial port or two master clock cycles before new data becomes available if the CS pin

is inactive (high); or two master clock cycles before new data becomes available if the user

holds CS low but has not started reading the data from the converter when in SEC mode.

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DS768PP1

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