CS5540-AS 查看數據表（PDF） - Cirrus Logic

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CS5540-AS

Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC

Cirrus Logic 

3. PIN DESCRIPTIONS

AIN1+ 1

AIN1- 2

VA- 3

VA+ 4

CS 5

SCLK 6

CHS 7

OSC1 8

16 AIN2+

15 AIN2-

14 VREF+

13 VREF-

12 DGND

11 VD+

10 SDO

9 OSC2

CS5540

Clock Generator

OSC1; OSC2 - Master Clock.

An inverting amplifier inside the chip is connected between these pins and can be used with a

crystal or resonator to provide the master clock for the device. Alternatively, an external

(CMOS compatible) clock (powered relative to VD+) can be supplied into the OSC1 pin to

provide the master clock for the device and the OSC2 pin can be left unconnected.

Control Pins and Serial Data I/O

CS - Chip Select.

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should only be changed when SCLK = 0.

SDO - Serial Data Output.

SDO is the serial data output. It will output a high impedance state if CS = 1.

SCLK - Serial Clock Input.

A clock signal on this pin determines the output rate of the data for the SDO pins respectively.

This input is a Schmitt trigger to allow for slow rise-time signals. The SCLK pin will recognize

clocks only when CS is low.

CHS - Channel Select Input.

CHS permits the user to select between AIN1 and AIN2 for data conversions. When CHS = 0,

AIN1 is converted. When CHS = 1, AIN2 is converted. Note that since the converter

continuously converts the input selected by CHS, the channel being converted can be switched

at any time. The current conversion will be aborted and a new one started on the newly

selected channel. The serial data status flags will indicate which channel was converted.

DS503PP1

17

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