CS5529-AS 查看數據表（PDF） - Cirrus Logic

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CS5529-AS

16-bit, Programmable ∆Σ ADC with 6-bit Latch

Cirrus Logic 

CS5529

PIN DESCRIPTIONS

NEGATIVE ANALOG POWER VA- 1

POSITIVE ANALOG POWER VA+ 2

DIFFERENTIAL ANALOG INPUT AIN+ 3

DIFFERENTIAL ANALOG INPUT AIN- 4

LOGIC OUTPUT (ANALOG) A0 5

LOGIC OUTPUT (ANALOG) A1 6

LOGIC OUTPUT (DIGITAL) D0 7

CHIP SELECT CS 8

SERIAL CLOCK INPUT SCLK 9

CRYSTAL OUT XOUT 10

20 VREF+ VOLTAGE REFERENCE INPUT

19 VREF- VOLTAGE REFERENCE INPUT

18 D3

LOGIC OUTPUT (DIGITAL)

17 D2

LOGIC OUTPUT (DIGITAL)

16 D1

LOGIC OUTPUT (DIGITAL)

15 SDI SERIAL DATA INPUT

14 SDO SERIAL DATA OUTPUT

13 VD+ POSITIVE DIGITAL POWER

12 DGND DIGITAL GROUND

11 XIN CRYSTAL IN

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 10, 11.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device. Alternatively, an external (CMOS compatible) clock (powered

relative to VD+) can be supplied into the XIN pin to provide the master clock for the device.

Control Pins and Serial Data I/O

CS - Chip Select, Pin 8.

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should be changed when SCLK = 0.

SDI - Serial Data Input, Pin 15.

SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.

SDO - Serial Data Output, Pin 14.

SDO is the serial data output. It will output a high impedance state if CS = 1.

SCLK - Serial Clock Input, Pin 9.

A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins

respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin

will recognize clocks only when CS is low.

26

DS246F5

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