CS53L21-DNZR 查看數據表（PDF） - Cirrus Logic

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CS53L21-DNZR

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

6.17 Status (Address 20h) (Read Only)

7

6

5

Reserved SP_CLKERR Reserved

4

Reserved

3

Reserved

2

1

0

Reserved ADCA_OVFL ADCB_OVFL

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

register was last read. A ”0” means the associated error condition has NOT occurred since the last reading

of the register. Reading the register resets all bits to 0.

Serial Port Clock Error (SP_CLK Error)

Default: 0

Function:

Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 29“Serial Port Clocking” on

page 29 for valid clock ratios.

Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.

ADC Overflow (ADCX_OVFL)

Default = 0

Function:

Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the

associated ADC’s.

DS700PP1

55

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