CS53L21-DNZR 查看數據表（PDF） - Cirrus Logic
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CS53L21-DNZR Datasheet PDF : 66 Pages
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CS53L21
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
Addr Function
7
6
5
4
3
2
1
01h ID
p 40
default
02h Power Ctl. 1
Chip_ID4
1
Reserved
Chip_ID3
1
Chip_ID2
0
Chip_ID1
1
Chip_ID0
1
Rev_ID2
0
Rev_ID1
0
Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA
p 40
default
03h Speed Ctl. &
Power Ctl. 2
0
AUTO
1(See Note 1(See Note 2
2 on page on page 40)
40)
SPEED1 SPEED0
0
3-ST_SP
0
0
PDN_MICB PDN_MICA
0
PDN_
MICBIAS
p 41
default
1
0
1
0
1
1
1
04h Interface Ctl.
p 43
default
Reserved
0
M/S
Reserved Reserved Reserved ADC_I²S/LJ DIGMIX
0
0
0
0
0
0
05h MIC Control ADC_SNGVOL ADCB_
& Misc.
DBOOST
ADCA_
DBOOST
MICBIAS_ MICBIAS_ MICBIAS_
SEL
LVL1
LVL0
MICB_
BOOST
p 44
default
0
0
0
0
0
0
0
06h ADC Control
p 45
default
ADCB_HPF
EN
1
ADCB_HP
FRZ
0
ADCA_HPF
EN
1
ADCA_HP
FRZ
0
SOFTB
0
ZCROSSB
0
SOFTA
0
07h ADC Input
Select
, Invert, Mute
AINB_MUX1
AINB_MUX AINA_MUX1 AINA_MUX0 INV_ADCB
0
INV_ADCA
ADCB_
MUTE
p 47
default
0
0
0
0
0
0
0
08h Reserved
default
Reserved
0
Reserved
1
Reserved
1
Reserved
0
Reserved
0
Reserved
0
Reserved
0
09h SPE Control
Reserved
SPE_
ENABLE
FREEZE
Reserved
Reserved
Reserved SPE_SZC1
p 48
default
0Ah ALCA SZC &
PGAA Vol-
ume
0
ALCA_SR
DIS
0
0
ALCA_ZC
DIS
Reserved
0
PGAA
VOL4
0
PGAA
VOL3
1
PGAA
VOL2
1
PGAA
VOL1
p 49
default
0Bh ALCB SZC &
PGAB Vol-
ume
0
ALCB_SR
DIS
0
0
ALCB_ZC
DIS
Reserved
0
PGAB
VOL4
0
PGAB
VOL3
0
PGAB
VOL2
0
PGAB
VOL1
p 49
default
0Ch ADCA Atten-
uator
0
ADCA_
ATT7
0
ADCA_
ATT6
0
ADCA_
ATT5
0
ADCA_
ATT4
0
ADCA_
ATT3
0
ADCA_
ATT2
0
ADCA_
ATT1
p 50
default
0
0
0
0
0
0
0
0Dh ADCB Atten-
uator
ADCB_
ATT7
ADCB_
ATT6
ADCB_
ATT5
ADCB_
ATT4
ADCB_
ATT3
ADCB_
ATT2
ADCB_
ATT1
0
Rev_ID0
1
PDN
0
MCLKDIV2
0
MICMIX
0
MICA_
BOOST
0
ZCROSSA
0
ADCA_
MUTE
0
Reserved
0
SPE_SZC0
0
PGAA
VOL0
0
PGAB
VOL0
0
ADCA_
ATT0
0
ADCB_
ATT0
DS700PP1
37
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