CS53L21 查看數據表（PDF） - Cirrus Logic

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CS53L21

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

4.9 Recommended Power-Down Sequence

To minimize audible pops when turning off or placing the A/D in standby,

1. Mute the ADC’s.

2. Set the PDN bit in the power control register to ‘1’b. The A/D will not power down until it reaches a fully

muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to

disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.

3. Bring RESET low.

No Power

1. No audio signal

generated.

Off Mode (Power Applied)

1. No audio signal generated.

2. Control Port Registers reset

to default.

RESET = Low? Yes

No

Control Port

Active

No Control Port Valid Yes

Write Seq. within

10 ms?

PDN bit = '1'b? Yes

No

No

Valid

MCLK Applied?

20 ms delay

Charge Caps

1. VQ Charged to

quiescent voltage.

2. Filtx+ Charged.

ADC Initialization

2048 internal

MCLK cycle delay

Standby Mode

1. No audio signal generated.

2. Control Port Registers retain

settings.

Power Off Transition

1. Audible pops.

Hardware Mode

Minimal feature

set support.

Reset Transition

1. Pops suppressed.

ERROR: Power removed

Software Mode

Registers setup to

desired settings.

Sub-Clocks Applied

1. LRCK valid.

2. SCLK valid.

3. Audio samples

processed.

No

Valid

MCLK/LRCK

Ratio?

Yes

RESET = Low

Normal Operation

Audio signal generated per control port or stand-

alone settings.

PDN bit set to '1'b

(software mode only)

Figure 17. Initialization Flow Chart

DS700PP1

33

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