CS53L21 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS53L21 Datasheet PDF : 66 Pages
| |||
POWER CONSUMPTION
See (Note 17)
Power Ctl. Registers
02h
03h
CS53L21
Typical Current (mA)
Operation
V
1 Off (Note 18)
x x x x x x x x x x 1.8
2.5
2 Standby (Note 19)
x x x x x x 1 x x x 1.8
2.5
3 Mono Record
ADC 1 1 1 1 1 0 0 1 1 1 1.8
2.5
PGA to ADC 1 1 1 0 1 0 0 1 1 1 1.8
2.5
MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 0 1.8
(with Bias)
2.5
MIC to PGA to ADC 1 1 1 0 1 0 0 1 0 1 1.8
(no Bias)
2.5
4 Stereo Record
ADC 1 1 1 1 0 0 0 1 1 1 1.8
2.5
PGA to ADC 1 1 0 0 0 0 0 1 1 1 1.8
2.5
MIC to PGA to ADC 1 1 0 0 0 0 0 0 0 1 1.8
(no Bias)
2.5
iVA
iVD
iVL
(Note 20)
Total
Power
(mWrms)
0
0
0
0
0
0
0
0
0.01 0.02
0
0.05
0.01 0.03
0
0.10
1.85
2.03
0.03
7.05
2.07 3.05
0.05
12.94
2.35
2.03
0.03
7.95
2.58 3.08
0.05
14.29
3.67 2.05
0.03
10.36
3.95 3.09
0.05
17.71
3.27 2.03
0.03
9.61
3.52 3.08
0.05
16.62
2.69 2.12
0.03
8.72
2.93 3.18
0.04
15.40
3.65 2.12
0.03
10.45
3.91 3.17
0.04
17.84
5.48 2.11
0.03
13.73
5.76 3.17
0.04
22.45
17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-
ter/slave operation.
18. RESET pin 25 held LO, all clocks and data lines are held LO.
19. RESET pin 25 held HI, all clocks and data lines are held HI.
20. VL current will slightly increase in master mode.
DS700PP1
19
Share Link: 