CS5461A-IS 查看數據表（PDF） - Cirrus Logic

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CS5461A-IS

Single Phase, Bi-directional Power/Energy IC

Cirrus Logic 

CS5461A

6.15 Pulsewidth Register ( PW )

Address: 21

MSB

LSB

223 222 221 220 219 218 217 216 .....

26

25

24

23

22

21

20

Default = 0x000200 = 512 sample periods

PW sets the pulsewidth of E1 and E2 pulses in Alternate Pulse and Mechanical Counter format. The width is a

function of number of sample periods. The default corresponds to a pulsewidth of

512 samples/[(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. The value is represented in un-

signed notation.

6.16 E3 Pulse Width Register ( PulseWidth )

Address: 22

MSB

LSB

0

222 221 220 219 218 217 216 .....

26

25

24

23

22

21

20

Default = 0x000000 = Hardware-generated pulse width (up to 125 µs)

The PulseWidth register sets the pulse width of E3 pulses in units of 1/OWR.

E3 pulse width =

----------P---u---l-s---e---W-----i-d---t--h----------

((MCLK) ⁄ K) ⁄ 1024

The range of this register is from 1 to 8388607.

6.17 Voltage Sag Duration Register ( VSAGDuration )

Address: 23

MSB

LSB

0

222 221 220 219 218 217 216 .....

26

25

24

23

22

21

20

Default = 0x000000

Voltage Sag Duration (VSAGDuration) defines the number of instantaneous voltage measurements utilized to de-

termine a voltage level sag event (VSAGLEVEL). Setting this register to zero will disable Voltage Sag-detect. The

value is represented in unsigned notation.

6.18 Voltage Sag Level Register ( VSAGLevel )

Address: 24

MSB

LSB

0

2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default = 0x000000

Voltage Sag Level (VSAGLevel) defines the voltage level that the magnitude of input samples, averaged over the

sag duration, must fall below in order to register a sag condition. This value is represented in unsigned notation

and in the range of 0 ≤ VSAGLevel < 1.0, with the binary point to the right of the MSB.

DS661F2

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