CS5464-IS 查看數據表（PDF） - Cirrus Logic
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CS5464-IS Datasheet PDF : 46 Pages
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CS5464
VOLTAGE x10
2nd Order
∆Σ
Modulator
SINC 3
X
IIR
Digital Filter SYSGain
Control Register
PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]
7
to Voltage
Channel 2
DELAY
REG
VDCoff
+
+Σ
Vgn
X
APF
HHPF
2322 ...
VHPF IHPF
6
5
... 3 2 1 0
Operational Modes Register
V
IIR
X
ε
X
2π
X
P
VQ
X
Q
CURRENT PGA
4th Order
∆Σ
Modulator
DELAY
REG
SINC 3
X
IIR
Digital Filter
SYSGain
+Σ
X
HPF
+
APF
I
IDCoff I gn
Figure 3. Data Measurement Flow Diagram
REGISTER NAMES INDICATED
IN SHADED AREAS.
4. THEORY OF OPERATION
The CS5464 is a four-channel analog-to-digital convert-
er (ADC) followed by a computation engine that per-
forms power calculations and energy-to-pulse
conversion. The data flow for the voltage and current
channel measurement and the power calculation algo-
rithms are depicted in Figures 3, 4, and 5.
The CS5464 analog inputs are structured with two Cur-
rent channels and two Voltage channels, then optimized
to simplify interfacing to various sensing elements. As
shown in Figures 3 and 4, the current channels are fully
independent while the two voltage channels are multi-
plexed.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is sub-
ject to a gain of 10x. A second-order delta-sigma modu-
lator samples the amplified signal for digitization.
Simultaneously, the current-sensing elements introduce
a voltage waveform on the two current channel inputs
IIN± and IIN2±, which is subject to the two selectable
gains of the programmable gain amplifier (PGA). The
amplified signals are sampled by a fourth-order
delta-sigma modulator for digitization. The converters
sample at a rate of MCLK/8. The over-sampling pro-
vides a wide dynamic range and simplified anti-alias fil-
ter design.
4.1 Digital Filters
The decimating digital filters on the four channels are
Sinc3 filters followed by 4th-order IIR filters. The sin-
gle-bit data is passed to the low-pass decimation filter
and output at a fixed word rate. The output word is
passed to an IIR filter to compensate for the magnitude
roll off of the low-pass filtering operation.
An optional digital high-pass filter (HPF in Figures 3 and
4) removes any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
Temp
Sensor
from Voltage Channel 1
2nd Order
∆Σ
Modulator
SINC 3
X
IIR
Digital Filter SYSGain
DELAY
REG
V2 dcoff
+
+Σ
V2gn
X
APF
HHPPF
V2
IIR
X
V2Q
X
Q2
Temperature
Registers
Control Register
PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]
7
2322 ...
VHPF IHPF
8
7
... 3 2 1 0
Operational Modes Register
ε
X
π
X
P2
CURRENT 2 PGA
4th Order
∆Σ
Modulator
DELAY
REG
SINC 3
X
IIR
Digital Filter
SYSGain
+Σ
X
HPF
I2
+
APF
I2 dcoff I2gn
Figure 4. Data Measurement Flow Diagram
REGISTER NAMES INDICATED
IN SHADED AREAS.
14
DS682PP1
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