CS5464(2007) 查看數據表（PDF） - Cirrus Logic

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CS5464
(Rev.:2007)

Three-channel, Single-phase Power/Energy IC

Cirrus Logic 

CS5464

8.2.7 Peak Current (I1PEAK, I2PEAK ) and Peak Voltage (V1PEAK, V2PEAK )

Address: 18 (I1PEAK), 19 (V1PEAK), 22 (I2PEAK), 23 (V2PEAK)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Peak current, I1PEAK (I2PEAK) and peak voltage, V1PEAK (V2PEAK) are the instantaneous current and voltage

samples with the greatest magnitude detected during the last low-rate interval. These are two's complement

values in the range of -1.0 ≤ value < 1.0, with the binary point to the right of the MSB.

8.2.8 Apparent Power (S1, S2)

Address: 20 (S1), 24 (S2)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Apparent power S1 (S2) is the product of V1RMS and I1RMS (V2RMS and I2RMS), These are two's complement

values in the range of 0 ≤ value < 1.0, with the binary point to the right of the MSB.

8.2.9 Power Factor (PF1, PF2)

Address: 21 (PF1), 25 (PF2)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Power factor is calculated by dividing active power by apparent power. The sign is determined by the active

power sign. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the binary point to the

right of the MSB.

8.2.10 Temperature (T) – Address: 27

MSB

LSB

-(27) 26

25

24

23

22

21

20

..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16

T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale, and is a

two's complement value in the range of -128.0 ≤ value < 128.0 (oC), with the binary point to the right of bit 16.

T can be rescaled by the application using the TGAIN and TOFF registers.

8.2.11 Active, Apparent, and Reactive Energy Pulse Outputs (EPULSE, SPULSE, QPULSE )

Address: 29 (EPULSE), 30 (SPULSE), 31 (QPULSE)

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

These drive the pulse outputs when configured to do so. If the Ichan bit in Modes is “0”, these registers are

driven from P1AVG, S1, and Q1AVG, respectively. If the Ichan bit is “1”, these registers are driven from P2AVG,

S2, and Q2AVG, respectively. These are two's complement values in the range of -1.0 ≤ value < 1.0, with the

binary point to the right of the MSB.

30

DS682F1

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