CS5461-IS 查看數據表（PDF） - Cirrus Logic

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CS5461-IS

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

VDCoff* V gn *

V*

V ACoff*

VOLTAGE

PGA

∆Σ

DELAY

REG

SINC 3

DELAY

REG

4th-order

IIR

HPF

+

+Σ

x

-

x +Σ

ΣN

N

÷N

V RMS*

Configuration Register *

PC[6:0] Bits

Poff*

-

x +Σ

PulseRateF *

x

TBC *

Energy -

to - Pulse

Fout

x

ΣN

÷N

P*

x

Energy -

to - Pulse

PulseRateE*

PAvg*

Eout

E dir

CURRENT

PGA ∆Σ

SINC 3

4th-order

IIR

HPF

+Σ

x

+

IDCoff* I gn *

x +Σ

-

ΣN

I*

IACoff*

N

÷N

I RMS *

* DENOTES REGISTER NAME

Figure 2. Data Flow.

the voltage/current channel inputs are subject to the 3.1.3 Digital High-Pass Filters

gains of the input PGAs. These waveforms are then

sampled by the delta-sigma modulators at a rate of

(MCLK/K) / 8.

Both channels provide an optional high-pass filter

(“HPF” in Figure 2) which can be engaged into the

signal path, in order to remove the DC content from

3.1.1 High-Rate Digital Low-Pass Fil-

ters

The data is then low-pass filtered, to remove

the current/voltage signal before the RMS/energy

calculations are made. These filters are activated by

enabling certain bits in the Configuration Register.

high-frequency noise from the modulator output. 3.1.4 Gain and DC Offset Adjustment

Referring to Figure 2, the high rate filters on both

channels are implemented as fixed Sinc3 filters.

After the filtering, the instantaneous voltage and

current digital codes are both subjected to value ad-

Also note from Figure 2 that the digital data on the justments, based on the values in the DC Offset

voltage channel is subjected to a variable time-de- Registers (additive) and the Gain Registers (multi-

lay filter. The delay depends on the value of the plicative). These registers are used for calibration

seven phase compensation bits (see Phase Com- of the device (see Section 4.4, Calibration). After

pensation) set in the configuration register.

offset and gain, the data is available to the user by

3.1.2 Digital Compensation Filters

reading the Instantaneous Voltage and Current

Registers.

The data from both channels is then passed through

two 4th-order IIR “compensation” filters, whose

purpose is to correct (compensate) for the magni-

3.1.5 Average (Real) Power Computa-

tion

tude roll-off of the low-pass filtering operation. The digital instantaneous voltage and current data

These filters “re-flatten” the magnitude response of is then processed further. Referring to Figure 2, the

the I and V channels over the relevant frequency instantaneous voltage/current data samples are

range, by correcting for the magnitude roll-off ef- multiplied together (one multiplication for each

fects that are induced onto the I and V signal spec- pair of voltage/current samples) to form instanta-

trums by the Sinc3 low-pass filter stages.

neous power data. The instantaneous power data is

then averaged over N instantaneous conversions

(N = value in Cycle Count Register) to form the re-

sult in the Average Power Register. The average

14

DS546F2

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