CS5461
SWITCHING CHARACTERISTICS
Parameter
Symbol Min
Typ
Max Unit
Master Clock Frequency Internal Gate Oscillator (Note 10) MCLK
2.5
4.096
20
MHz
Master Clock Duty Cycle
40
-
60
%
CPUCLK Duty Cycle
(Note 11)
40
60
%
Rise Times
(Note 12)
Any Digital Input Except SCLK trise
-
SCLK
-
-
1.0
µs
-
100
µs
Any Digital Output
-
50
-
ns
Fall Times
(Note 12)
Any Digital Input Except SCLK tfall
SCLK
Any Digital Output
-
-
1.0
µs
-
-
100
µs
-
50
-
ns
Start-up
Oscillator Start-Up Time
XTAL = 4.096 MHz (Note 13) tost
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2
MHz
Serial Clock
Pulse Width High
t1
Pulse Width Low
t2
200
-
200
-
-
ns
-
ns
SDI Timing
CS Falling to SCLK Rising
t3
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t4
50
-
-
ns
Data Hold Time After SCLK Rising
t5
100
-
-
ns
SDO Timing
CS Falling to SDI Driving
t7
-
20
50
ns
SCLK Falling to New Data Bit (hold time)
t8
-
20
50
ns
CS Rising to SDO Hi-Z
t9
-
20
50
ns
Auto-Boot Timing
Serial Clock
Pulse Width High t10
Pulse Width Low
t11
8
MCLK
8
MCLK
MODE setup time to RESET Rising
t12
50
ns
RESET rising to CS falling
t13
48
MCLK
CS falling to SCLK rising
t14
100
8
MCLK
SCLK falling to CS rising
t15
16
MCLK
CS rising to driving MODE low (to end auto-boot sequence).
t16
50
ns
SDO guaranteed setup time to SCLK rising
t17
100
ns
Notes: 10. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must
remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, full XIN frequency range is
2.5 MHz - 20 MHz.
11. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.
12. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
13. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
3.1 Theory of Operation
A computational flow diagram for the two data
paths is shown in Fig. 2. The analog waveforms at
12
DS546F2