CS5371A-ISZ(2006) 查看數據表（PDF） - Cirrus Logic

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CS5371A-ISZ
(Rev.:2006)

Low-power, High-performance ∆Σ Modulators

Cirrus Logic 

CS5371A CS5372A

VREF+ _ Positive Voltage Reference Input, pin 5

Input for an external +2.500 V voltage reference relative to VREF-.

VREF- _ Negative Voltage Reference Input, pin 6

This pin should be tied to VA- near the voltage reference output.

Digital Inputs

MCLK _ Modulator Clock Input, pin 19

A CMOS compatible clock input for the modulator internal master clock, nominally 2.048 MHz

with an amplitude equal to the VD digital power supply.

MSYNC _ Modulator Sync Input, pin 20

A low to high transition resets the internal clock phasing of the modulator. This assures the

sampling instant and modulator data output are synchronous to the external system.

OFST _ Offset Mode Select, pin 14

When high, adds approximately -60 mV or -35 mV of internal differential offset to the analog

input signal to guarantee any ∆Σ idle tones are removed. When low, no offset is added.

PWDN _ Power-down Mode, pin 24

When high, the modulator is in power-down mode. Halting MCLK while in power down mode

reduces modulator power dissipation further.

Digital Outputs

MDATA _ Modulator Data Output, pin 21

Modulator data is output as a 1-bit serial data stream at 512 kHz with an MCLK input of

2.048 MHz.

MFLAG _ Modulator Flag Output, pin 22

A high level output indicates the modulator is unstable due to an over-range on the analog

inputs.

DS748F1

27

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