CS5340-DZZ 查看數據表（PDF） - Cirrus Logic
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CS5340-DZZ Datasheet PDF : 22 Pages
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Confidential Draft
3/11/08
CS5340
4.2.3 Master Clock
The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the speed mode and
frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.
Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note
that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x
for Single-, Double-, and Quad-Speed Modes, respectively).
Single-Speed Mode
MCLK/LRCK Ratio
256x, 512x
* Quad Speed, 64x only available in Master Mode.
Double-Speed Mode
128x, 256x
Quad-Speed Mode
64x*,128x
Table 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz)
32
44.1
48
64
88.2
96
192
MCLK (MHz)
8.192
11.2896
22.5792
12.288
24.576
8.192
11.2896
22.5792
12.288
24.576
12.288
24.576
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3 Serial Audio Interface
The CS5340 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5340 will detect
the logic level on SDOUT (pin 4). A 10 kΩ pull-up to VL is needed to select I²S format, and a 10 kΩ pull-
down to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the I²S and Left-Justified
audio formats. Please see Figures 13 through 16, for more information on the required timing for the two
serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audio
interface formats.
LRCK
Left Channel
R ight Channel
SCLK
SDATA
23 22 9 8 7 6 5 4 3 2 1 0
23 22 9 8 7 6 5 4 3 2 1 0
Figure 19. I²S Serial Audio Interface
23 22
LRCK
Left Channel
SCLK
SDATA
23 22 9 8 7 6 5 4 3 2 1 0
R ight C hannel
23 22 9 8 7 6 5 4 3 2 1 0
Figure 20. Left-Justified Serial Audio Interface
23 22
DS601F2
17
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