CS5320-KL1 查看數據表（PDF） - Cirrus Logic
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CS5320-KL1 Datasheet PDF : 38 Pages
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CS5320/21/22
2. GENERAL DESCRIPTION
The CS5320 and CS5321 are fourth-order CMOS
monolithic analog modulators designed specifical-
ly for very high resolution measurement of signals
between dc and 1500 Hz. Configuring the CS5320
or CS5321 with the CS5322 FIR filter results in a
high resolution A/D converter system that performs
sampling and A/D conversion with dynamic range
exceeding 120 dB .
The CS5320 and CS5321 use a fourth-order over-
sampling architecture to achieve high resolution
A/D conversion. The modulator consists of a 1-bit
A/D converter embedded in a negative feedback
loop. The modulator provides an oversampled seri-
al bit stream at 256 kbits per second (HBR=1) and
128 kbits per second (HBR=0) operating with a
clock rate of 1.024 MHz. Figure 18 illustrates the
CS5320/CS5321 Block Diagram.
The CS5322 is a monolithic digital Finite Impulse
Response (FIR) filter with programmable decima-
tion. The CS5322 and CS5320/CS5321 are intend-
ed to be used together to form a unique high
dynamic range ADC chipset. The CS5322 provides
the digital anti-alias filter for the CS5320/CS5321
modulator output. The CS5322 consists of: a multi-
stage FIR filter, four registers (status, data, offset,
and configuration), a flexible serial input and out-
put port, and a 2-channel input data multiplexer
that selects data from the CS5320/CS5321 (MDA-
TA) or user test data (TDATA). The CS5322 deci-
mates (64x to 4096x) the output to any of seven
selectable up-date periods: 16, 8, 4, 2, 1, 0.5 and
0.25 milliseconds. Data is output from the digital
filter in a 24-bit serial format. Figure 19 illustrates
the CS5322 Block Diagram.
AINR
AIN+
AIN-
Vdd1
Vss1
AGND
Vdd2
Vss2
Osc.
Detect
Digital
Control
DGND
LPWR
OFST
MFLG
VREF+
VREF-
Σ
A/D
D/A
Clock
Generation
HBR
MCLK
MSYNC
MDATA
MDATA
Figure 18. CS5320/21 Block Diagram
16
DS454PP1
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