CS5181 查看數據表（PDF） - Cirrus Logic
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CS5181 Datasheet PDF : 24 Pages
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PIN DESCRIPTIONS
Analog Ground
AGND
Pos. Reference VREF+
Neg. Reference
VREF-
Reference Output VREFOUT
Pos. Reference Input VREFIN
Reference Bypass VREFCAP
Analog Ground
AGND
Analog Supply
VA2+
Invalid Conversion MFLAG
Sync. Filter
SYNC
Digital Ground
DGND
Pos. Digital Supply
VD2+
Inverse Serial Clock
SCLK
Serial Clock
SCLK
Analog Ground
AGND
Pos. Reference VREF+
Neg. Reference
VREF-
Reference Output VREFOUT
Analog Ground
AGND
Analog Ground
AGND
Reference Input VREFIN
Reference Bypass VREFCAP
Analog Ground
AGND
Analog Ground
AGND
Analog Supply
VA2+
Analog Supply
VA2+
Invalid Conversion MFLAG
Sync. Filter
SYNC
Digital Ground
DGND
Digital Ground
DGND
Pos. Digital Supply
VD2+
Pos. Digital Supply
VD2+
Digital Ground
DGND
Inverse Serial Clock
SCLK
Serial Clock
SCLK
DS250PP1
5
4 3 2 1 28 27 26
25
6
24
7
CS5181
23
8
22
9
21
10
20
11
12
13
14
15
16
17
18
19
4443424140393837363534
1
33
2
32
3
31
4
30
5
6
CS5181
29
28
7
27
8
26
9
25
10
24
11
23
12131415 16171819202122
CS5181
VA1+ Positive Analog Supply
AIN- Negative Analog Input
AIN+ Positive Analog Input
PWDN Power Down Mode
MODE Modulator Only Mode
RESET Reset and Calibration
DGND Digital Ground
VD1+ Positive Digital Supply
MCLK Master Clock
MCLK Inverse Master Clock
AGND Analog Ground
FSO Frame Sync Output
SDO Serial Data Out
SDO Inverse Serial Data Out\
AGND Analog Ground
VA1+ Positive Analog Supply
AGND Analog Ground
AIN- Negative Analog Input
AIN+ Positive Analog Input
AGND Analog Ground
PWDN Power Down Mode
MODE Modulator Only Mode
RESET Reset and Calibration
DGND Digital Ground
DGND Digital Ground
VD1+ Positive Digital Supply
VD1+ Positive Digital Supply
DGND Digital Ground
MCLK Master Clock
MCLK Inverse Master Clock
DGND Digital Ground
NC
AGND Analog Ground
NC
FSO Frame Sync Output
SDO Serial Data Out
SDO Inverse Serial Data Out\
15
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