CS5101A 查看數據表（PDF） - Cirrus Logic

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CS5101A

16-bit, 100 kSps / 20 kSps A/D Converters

Cirrus Logic 

CS5101A CS5102A

RST

STBY

trst

tcal

tdrrs

Reset and Calibration Timing

C H 1 /2

T R K 1 ,T R K 2

T R K 1 ,T R K 2

tdrsh1

tdfsh4

a. FRN Mode

HOLD

S S H /S D L

tdfsh2

tdrsh

S S H ,T R K 1 ,T R K 2

T R K 1 ,T R K 2

tdfsh1

b. PDT, RBT Mode

Control Output Timing

C H 1 /2

tdhlri

HOLD

thold

Channel Selection Timing

thcf

C L K IN

HOLD

Start Conversion Timing

Figure 1. Reset, Calibration, and Control Timing

10

DS45F6

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