CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
PCP_A[3:0]
PCP_AD[7:0]
PCP_CS
PCP_WR
t mas
t mrwsu
t mah
LSP
t mdhr
t mdd
t mcdr
t mrpw
t mdis
t mrd
MSP
t mrwhld
t mrdtw
PCP_DS
tmrwirqh
PCP_IRQ
Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing
Y PCP_A[3:0]
R PCP_AD[7:0]
A PCP_CS
IN PCP_WR
PCP_DS
IM PCP_IRQ
t mas
tmah
LSP
t mdsu
t mcdw
t mrwsu
t mdhw
MSP
t mwpw
t mwd
tmrwirql
t mrwhld
PREL Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing
t mwtrd
DS705PP6
Copyright 2009 Cirrus Logic
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